The invention relates generally to etching of materials. In particular, the invention relates to the plasma etching of both silicon nitride and silicon oxide.
The continuing level of integration in semiconductor integrated circuits has in large part been accomplished by the reduction in minimum feature size, often referred to as critical dimension (CD) with respect to a particular type of feature. Integrated circuits are now entering production based on a CD of 0.18 xcexcm. Further and significant decreases in CD are being planned.
The reduction in CD has been obtained not only by finer photolithography but also by more sophisticated processing. In etching features into an already formed partial structure, the etching is almost always done with dry plasma etching, and the dry etching process has been made to overcome problems introduced by the small feature sizes. In particular, the directionality of etching narrow holes in already formed features must be controlled for a variety of requirements. Typically, the holes should have a nearly vertical profile, but, in some cases, special etching profiles must be obtained.
An example of a special profile is a shallow trench isolation (STI), formed from the partially developed structure illustrated in the cross-sectional views of FIGS. 1 and 2. STI is intended to electrically isolate neighboring semiconductor transistors on the semiconductor chip. The more final structure is illustrated in FIG. 2. The vertical structure before lateral definition, illustrated in FIG. 1, includes a silicon substrate 10, a pad oxide layer 12 of about 15 nm thickness, a silicon nitride (Si3N4) layer 14 of about 150 nm thickness to act as a hard mask, and an anti-reflective coating (ARC) layer 16 of about 70 nm thickness and typically composed of silica although other compositions are used. The silicon substrate 10 is semiconducting, and active devices such as transistors are intended to be formed in it after the trench isolation. The pad oxide layer 12 provides adhesion to the silicon substrate 10 in view of the relatively poor adhesion of silicon nitride to silicon, and it further protects the underlying silicon during nitride removal. Oxide is the common descriptor for silicon oxide, usually having a composition close to silicon dioxide, often referred to as silica, but minor components of other elements may also be present. Nitride is a somewhat generic term for a material having a composition SiNx, where x may have values between about 1 and 1.5. The ARC layer 16 facilitates the subsequent photographic definition of the features. A photoresist layer 18 of about 400 nm thickness is deposited and defined into horizontally extending ridges 20. The ridge width is often the critical dimension.
A series of etch steps are then used to produce the structure illustrated in the cross-sectional view of FIG. 2 in which a trench 22 is etched deeply into the silicon substrate 10 between the two ridges defined by the patterned photoresist layer 18. An exemplary trench depth in the silicon is 350 to 500 nm. The etching of the ARC layer 16 is standard and will not be further discussed.
The nitride hard mask 14 is required because such a deep trench etch tends to etch the side of the photoresist 18 of FIG. 1, thus comprising the critical dimension. The nitride hard mask 14 is more resistant to such side etching. Nonetheless, it is desired that the photoresist 18 remain through the trench etch since its presence or absence substantially affects the overall etching chemistry. Thereafter, in steps not intimately connected with the invention, the photoresist 18 is removed, and oxide dielectric is filled into the trench 22 and over it. Several steps including chemical mechanical polishing remove the nitride layer 14 and oxide layer 12 and level the oxide dielectric at the top of the trench. The silicon ridges are thereby exposed between oxide-filled trenches, and transistor gates are formed on the exposed silicon. The oxide dielectric in the trenches 22 provides electrical isolation between the semiconductor devices formed in neighboring ridges.
As shown, it is desirable to etch the various layers in such a way as to form soft shoulders 24 at the top corner 26 of the trench 22. It has been observed that the top corners 26 formed between the silicon and the patterned oxide layer 12 critically affect the performance and reliability of the semiconductor devices formed in the adjacent top silicon surface. The degree of the shoulder shaping can be adjusted for different designs. The illustrated shaping represents one extreme. Other designs produce a more moderate, concave shape, rather than the illustrated convex shape, but a shape having a finite inward and downward slope away from the vertical.
Plasma chemistries for etching silicon with the desired profiles are well known. One type of recipe is based on hydrogen bromide (HBr), oxygen gas (O2), and chlorine gas (Cl2). However, the trench shoulder is in large part determined by the nitride open etch process piercing the nitride layer 14 because the nitride open etch tends to be relatively unselective to the underlying silicon, with selectivities of etching nitride relative to silicon of less than unity being typically observed, and an extensive over etch is required to guarantee that the nitride has been opened. That is, the nitride open process inevitably etches somewhat into the silicon, and this initial silicon etching significantly influences the shape of the shoulder 24 adjacent the oxide-silicon corner 26.
At the present time, there are two popular recipes for the nitride open, neither of which produces the desired shoulder 24. A first recipe uses a single step for plasma etching both the nitride hard mask 14 and the underlying oxide layer 12 based on the etching gas combination SF6/HBr with strong wafer biasing during etching. This chemistry and strong biasing produce an anisotropic etch of the nitride and oxide, as illustrated in the cross-sectional view of FIG. 3. However, it produces a generally isotropic etch of silicon. As a result, upon breakthrough of the nitride/oxide layer, an incipient trench 30 is formed having retrograde sidewalls 32 underlying the oxide layer 12 and having an acute corner 34 between the silicon and oxide. A second recipe is broken into two steps. The first step uses the SF6/HBr etching gas only part way through the oxide layer 12. Then, to produce the structure illustrated in the cross-sectional view of FIG. 4, a CF4/Ar plasma etching gas is used with substantial wafer biasing to produce a strongly isotropic etch resulting in an incipient trench 36 having a vertical profile. The exposed oxide-silicon corner 38 is approximately vertical and flat and is exposed during the subsequent silicon etching. For some applications, it is desired to form nearly vertical trench sidewalls in the silicon layer 10, but they should not extend up to the oxide layer 12. In other applications, trench tapering is desired to facilitate oxide backfilling. However, with decreasing spacing between features, the taper angle must be raised closer to the 90xc2x0 vertical profile.
We have tried adding CF4 to the SF6/HBr etching gas. The nitride etch rate and CD control are improved, but the photoresist selectivity still remains significantly below unity.
Accordingly, a plasma etching process is desired to etch silicon nitride and silicon oxide with enhanced photoresist selectivity and producing a rounded corner between the oxide and underlying silicon.
The invention includes a nitride plasma etching process using an etching gas mixture principally composed of sulfur hexafluoride (SF6) and a weakly polymerizing hydrofluorocarbon, the preferred example of which is trifluoromethane (CHF3).
The process is preferably performed in a plasma reactor having a decoupled plasma source and an RF biased pedestal electrode supporting the substrate being etched. During the nitride etching process, the bias power is moderate, for example, 200 to 350 W for a 200 mm wafer, and preferably between about a third and a half of the plasma source power.
The nitride etching process is particularly useful when the nitride layer overlies a silicon layer with an oxide layer in between, and the corner of the oxide-silicon interface must be protected, for example, by a sloping upper surface of silicon next to the oxide layer. An example of such a structure is a trench etched in silicon, such as a shallow trench isolation.
In an integrated process of the invention of etching a trench underlying oxide and nitride layers, the nitride etch may be continued until it breaks through the oxide, and thereafter a bromine-based plasma etch process forms the trench. Alternatively, a separate oxide etch step may be used based on fluorine chemistry, particularly using a fluorocarbon such as carbon tetrafluoride. Preferably, the bias power is kept low during the oxide etch.
The integrated process is preferably performed in a single plasma reaction chamber.